The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Dec. 12, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Umberto Santoni, Scottsdale, AZ (US);

Rahul Pal, Bangalore, IN;

Philip Abraham, Burlingame, CA (US);

Mahesh Mamidipaka, Banglore, IN;

C Santhosh, Banglore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/273 (2006.01); G06F 11/16 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/273 (2013.01); G06F 11/1004 (2013.01); G06F 11/1629 (2013.01); G06F 11/1633 (2013.01); G06F 11/1641 (2013.01);
Abstract

A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.


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