The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Dec. 19, 2018
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Nozomu Harada, Tokyo, JP;

Hiroki Nakamura, Tokyo, JP;

Min Soo Kim, Leuven, BE;

Zheng Tao, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/11 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/76802 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 29/41741 (2013.01); H01L 29/66666 (2013.01);
Abstract

In an SRAM cell circuit, an N+ layerand a P+ layer, which are present between first gate connection W layersandconnecting to gate TiN layersandin plan view, which connect to the bottom portions of Si pillarsand, and which extend in the horizontal direction, connect through a second gate connection W layerto a first gate connection W layer, which connects to the gate TiN layersandand extend in the horizontal direction. The second gate connection W layerhas a bottom portion within the first gate connection W layer, and has an upper surface positioned lower than the upper surfaces of the gate TiN layerstoand the first gate connection W layersto


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