The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Jul. 09, 2019
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Ronghua Zhu, San Jose, CA (US);

Eric Ooms, San Jose, CA (US);

Xin Lin, San Jose, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/31144 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/7816 (2013.01);
Abstract

A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.


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