The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2020

Filed:

Aug. 30, 2018
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Keith Doran Weeks, Chandler, AZ (US);

Nyles Wynn Cody, Tempe, AZ (US);

Marek Hytha, Brookline, MA (US);

Robert J. Mears, Wellesley, MA (US);

Robert John Stephenson, Duxford, GB;

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/154 (2013.01); H01L 21/0245 (2013.01); H01L 21/02488 (2013.01); H01L 21/02507 (2013.01); H01L 21/02647 (2013.01); H01L 21/02694 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01);
Abstract

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.


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