The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Sep. 10, 2018
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Mrunmay Talegaonkar, Laguna Hills, CA (US);

Jorge Pernillo, Daly City, CA (US);

Junyi Sun, Singapore, SG;

Praveen Prabha, Lake Forest, CA (US);

Chang-Feng Loi, Singapore, SG;

Yu Liao, Longmont, CO (US);

Jamal Riani, Fremont, CA (US);

Belal Helal, Santa Clara, CA (US);

Karthik Gopalakrishnan, Cupertino, CA (US);

Aaron Buchwald, Newport Beach, CA (US);

Assignee:

INPHI CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/197 (2006.01); H04L 7/033 (2006.01); H03L 7/099 (2006.01); H03L 7/087 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03L 7/087 (2013.01); H03L 7/0807 (2013.01); H03L 7/099 (2013.01); H04L 7/0331 (2013.01);
Abstract

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.


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