The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jul. 29, 2016
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Hiroki Nakamura, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 23/535 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 23/535 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66666 (2013.01); H01L 29/66772 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01); H01L 29/0676 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 2029/7858 (2013.01);
Abstract

An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.


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