The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2020
Filed:
Sep. 25, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Yongjun Shi, Clifton Park, NY (US);
Ruilong Xie, Schenectady, NY (US);
Nan Fu, Ballston Lake, NY (US);
Chun Yu Wong, Clifton Park, NY (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Caymand, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/0273 (2013.01); H01L 21/28568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76819 (2013.01);
Abstract
A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.