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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10804148 B1

PDFFull Text
Date of Patent:
Oct. 13, 2020

Filed:

Aug. 25, 2017

Buried contact to provide reduced vfet feature-to-feature tolerance requirements

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Su Chen Fan, Cohoes, NY (US);

Jeffrey C. Shearer, Slingerlands, NY (US);

Robert C. Wong, Poughkeepsie, NY (US);

Ruilong Xie, Schenectady, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Joseph Petrokaitis

Primary Examiner:

Dung A Le

Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/535 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823885 (2013.01); H01L 23/535 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 27/1211 (2013.01); H01L 29/42392 (2013.01); H01L 29/4983 (2013.01); H01L 29/66666 (2013.01); H01L 29/66742 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H01L 21/823871 (2013.01); H01L 27/1104 (2013.01);
Abstract

Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.

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