The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jun. 07, 2019
Applicants:

Qualcomm Technologies, Incorporated, San Diego, CA (US);

Yonsei University, University-industry Foundation, Seoul, KR;

Inventors:

Seong-Ook Jung, Seoul, KR;

Byungkyu Song, Seoul, KR;

Sehee Lim, Seoul, KR;

Seung Hyuk Kang, San Diego, CA (US);

Sungryul Kim, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); H04L 9/32 (2006.01); G11C 11/412 (2006.01); G11C 11/16 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0081 (2013.01); H04L 9/3278 (2013.01); G11C 11/161 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract

Transistor noise tolerant, non-volatile (NV) resistance element-based static random access memory (SRAM) physically unclonable function (PUF) circuits and related systems and methods. In exemplary aspects, a transistor and its complementary transistor, such as a pull-up transistor and complement pull-down transistor or pull-down transistor and complement pull-up transistor, of the PUF circuit are replaced with passive NV resistance elements coupled to the respective output node and complement output node to enhance imbalance between cross-coupled transistors of the PUF circuit for improved PUF output reproducibility. The added passive NV resistance elements replacing pull-up or pull-down transistors in the PUF circuit reduces or eliminates transistor noise that would otherwise occur if the replaced transistors were present in the PUF circuit as a result of changes in temperature, voltage variations, and aging effect. The bit error rate of the PUF circuit is reduced by the reduction in transistor noise thereby improving PUF output reproducibility.


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