The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Jun. 03, 2019
Applicant:

Unity Semiconductor Corporation, Sunnyvale, CA (US);

Inventors:

Lawrence Schloss, Palo Alto, CA (US);

Julie Casperson Brewer, Hoboken, NJ (US);

Wayne Kinney, Emmett, ID (US);

Rene Meyer, Fremont, CA (US);

Assignee:

Unity Semiconductor Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/56 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 11/5685 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0028 (2013.01); H01L 27/24 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 45/08 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0073 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/56 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); G11C 2213/74 (2013.01); G11C 2213/76 (2013.01);
Abstract

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).


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