The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2020

Filed:

Aug. 21, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alaa R. Alameldeen, Hillsboro, OR (US);

Berkin Akin, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 1/329 (2019.01); G06F 13/42 (2006.01); G06F 1/3287 (2019.01); G06F 1/3206 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 1/3206 (2013.01); G06F 1/329 (2013.01); G06F 1/3287 (2013.01); G06F 9/48 (2013.01); G06F 9/485 (2013.01); G06F 9/4806 (2013.01); G06F 9/4843 (2013.01); G06F 9/4856 (2013.01); G06F 9/4881 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5027 (2013.01); G06F 13/4234 (2013.01);
Abstract

A device is configured to be in communication with one or more host cores via a first communication path. A first set of processing-in-memory (PIM) cores and a second set of PIM cores are configured to be in communication with a memory included in the device over a second communication path, wherein the first set of PIM cores have greater processing power than the second set of PIM cores, and wherein the second communication path has a greater bandwidth for data transfer than the first communication path. Code offloaded by the one or more host cores are executed in the first set of PIM cores and the second set of PIM cores.


Find Patent Forward Citations

Loading…