The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Jun. 06, 2017
Shanghai Ic R&d Center Co., Ltd., Shanghai, CN;
Hong Lin, Shanghai, CN;
SHANGHAI IC R&D CENTER CO., LTD, Shanghai, CN;
CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD., Chengdu, CN;
Abstract
A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile