The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2020

Filed:

Jul. 01, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hochul Lee, Los Angeles, CA (US);

Keejong Kim, Phoenix, AZ (US);

Anil Chowdary Kota, San Diego, CA (US);

Chulmin Jung, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01); G11C 7/14 (2006.01); G11C 7/00 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 7/227 (2013.01); G11C 7/00 (2013.01); G11C 7/06 (2013.01); G11C 7/14 (2013.01);
Abstract

In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.


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