The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jan. 10, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Feng-Pin Chen, Taichung, TW;

Te-Chia Ku, Taichung, TW;

Chien-Kwen Chen, Taichung, TW;

Chi-Chang Wu, Taichung, TW;

Cheng-Ming Ho, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G03F 7/20 (2006.01); H01L 23/544 (2006.01); H01L 21/68 (2006.01); G01N 23/2251 (2018.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G03F 7/70633 (2013.01); H01L 22/20 (2013.01); H01L 23/544 (2013.01); G01N 23/2251 (2013.01); G01N 2223/401 (2013.01); G01N 2223/418 (2013.01); H01J 2237/2816 (2013.01); H01L 21/682 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.


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Chen, Feng-Pin. (2020). Overlay structure and method of fabricating the same (U.S. Patent No. 10790205). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10790205

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