The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Oct. 02, 2018
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Hsun-Chung Kuang, Hsinchu, TW;
Yen-Chang Chu, Tainan, TW;
Cheng-Tai Hsiao, Tainan, TW;
Ping-Yin Liu, Yonghe, TW;
Lan-Lin Chao, Sindian, TW;
Yeur-Luen Tu, Taichung, TW;
Chia-Shiung Tsai, Hsinchu, TW;
Xiaomeng Chen, Baoshan Township, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.