The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Jun. 20, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Reshma Lal, Hillsboro, OR (US);

Gideon Gerzon, Zichron Yaakov, IL;

Baruch Chaikin, Misgav, IL;

Siddhartha Chhabra, Portland, OR (US);

Pradeep M. Pappachan, Hillsboro, OR (US);

Bin Xing, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/60 (2013.01); H04L 29/06 (2006.01); G06F 21/57 (2013.01); G06F 13/28 (2006.01); H04L 9/32 (2006.01); G06F 21/62 (2013.01); G06F 21/85 (2013.01); G09C 1/00 (2006.01); G06F 13/20 (2006.01); H04L 9/06 (2006.01); G06F 21/51 (2013.01);
U.S. Cl.
CPC ...
G06F 21/602 (2013.01); G06F 13/20 (2013.01); G06F 13/28 (2013.01); G06F 21/57 (2013.01); G06F 21/6218 (2013.01); G06F 21/6281 (2013.01); G06F 21/85 (2013.01); G09C 1/00 (2013.01); H04L 9/32 (2013.01); H04L 63/126 (2013.01); G06F 21/51 (2013.01); H04L 9/0637 (2013.01); H04L 9/3242 (2013.01); H04L 63/12 (2013.01);
Abstract

Technologies for trusted I/O include a computing device having a processor, a channel identifier filter, and an I/O controller. The I/O controller may generate an I/O transaction that includes a channel identifier and a memory address. The channel identifier filter verifies that the memory address of the I/O transaction is within a processor reserved memory region associated with the channel identifier. The processor reserved memory region is not accessible to software executed by the computing device. The processor encrypts I/O data at the memory address in response to invocation of a processor feature and copies the encrypted data to a memory buffer outside of the processor reserved memory region. The processor may securely clean the processor reserved memory region before encrypting and copying the data. The processor may wrap and unwrap programming information for the channel identifier filter. Other embodiments are described and claimed.


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