The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Jan. 31, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eng Huat Goh, Penang, MY;

Hoay Tien Teoh, Paya Terubong, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/117 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H05K 1/0213 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/10189 (2013.01);
Abstract

A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.


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