The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Jan. 31, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Haiting Wang, Clifton Park, NY (US);

Guowei Xu, Ballston Lake, NY (US);

Hui Zang, Guilderland, NY (US);

Yue Zhong, Ballston Lake, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/32137 (2013.01); H01L 21/32139 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.


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