The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
May. 23, 2016
Applicant:
Pulsic Limited, Bristol, GB;
Inventors:
Paul Clewes, Northumberland, GB;
Liang Gao, Gateshead, GB;
Jonathan Longrigg, Newcastle upon Tyne, GB;
Assignee:
Pulsic Limited, Bristol, GB;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 111/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2111/12 (2020.01);
Abstract
An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.