The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Nov. 28, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Fong-Yuan Chang, Hsinchu County, TW;

Sheng-Hsiung Chen, Hsinchu County, TW;

Po-Hsiang Huang, Tainan, TW;

Jyun-Hao Chang, Kaohsiung, TW;

Chun-Chen Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/522 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11875 (2013.01);
Abstract

A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.


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