The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Oct. 16, 2019
Applicant:

United Microelectronics Corp., Hsin-chu, TW;

Inventors:

Zih-Yu Chiu, Hsinchu, TW;

Hsin-Wen Chen, Hsinchu County, TW;

Ya-Nan Mou, Hsinchu, TW;

Yuan-Hui Chen, Hsinchu, TW;

Chung-Cheng Tsai, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 27/11 (2013.01);
Abstract

An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.


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