The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Nov. 01, 2018
Cadence Design Systems, Inc., San Jose, CA (US);
Christos Papameletis, Binghamton, NY (US);
Brian Edward Foutz, Charlottesville, VA (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Krishna Vijaya Chakravadhanula, Vestal, NY (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).