The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2020
Filed:
Jun. 28, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Eah Loon Alan Chuah, Tanjung Tokong, MY;
Hui Hui Ngu, Bayan Lepas, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H03K 19/17732 (2020.01); H03K 19/17728 (2020.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17744 (2013.01); H03K 19/1774 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01); H03K 19/17732 (2013.01);
Abstract
An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.