The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Dec. 23, 2017
Applicants:

Yutechnix, Inc., Saratoga, CA (US);

Champion Microelectronic Corp., Hsinchu, TW;

Inventors:

Haiping Dun, Fremont, CA (US);

Ho-Yuan Yu, Saratoga, CA (US);

Hung-Chen Lin, Hsinchu, TW;

Assignees:

Champion Microelectronic Corp., Hsinchu, TW;

Yutechnix, Inc., Saratoga, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/70 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8725 (2013.01); H01L 29/0692 (2013.01); H01L 29/70 (2013.01); H01L 29/7806 (2013.01); H01L 29/7813 (2013.01);
Abstract

Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N− epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N− epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions. In a further embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create yet another device with very high breakdown voltage and very low leakage current. This structure can be extended to multiple deep trenches and shallow trenches as well.


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