The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Jan. 09, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Yuping Ren, Clifton Park, NY (US);

Haigou Huang, Rexford, NY (US);

Ravi Prakash Srivastava, Clifton Park, NY (US);

Zhiguo Sun, Halfmoon, NY (US);

Qiang Fang, Ballston Lake, NY (US);

Cheng Xu, Dresden, DE;

Guoxiang Ning, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76813 (2013.01); H01L 21/31122 (2013.01); H01L 21/7681 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02266 (2013.01);
Abstract

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.


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