The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Nov. 13, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ken-Hsien Hsieh, Taipei, TW;

Wen-Li Cheng, Taipei, TW;

Dong-Yo Jheng, Hsinchu, TW;

Chih-Ming Lai, Hsinchu, TW;

Ru-Gun Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/308 (2006.01); G03F 7/20 (2006.01); G03F 1/70 (2012.01); G06F 30/39 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
H01L 21/3088 (2013.01); G03F 1/70 (2013.01); G03F 7/70425 (2013.01); G06F 30/39 (2020.01); G06F 30/398 (2020.01); G06F 2119/18 (2020.01);
Abstract

A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.


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