logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10770303 B1

PDFFull Text
Date of Patent:
Sep. 08, 2020

Filed:

Apr. 29, 2019

Mechanisms for forming patterns using multiple lithography processes

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Ming Chang, Hsinchu County, TW;

Ming-Feng Shieh, Tainan County, TW;

Chih-Ming Lai, Hsinchu, TW;

Ru-Gun Liu, Hsinchu County, TW;

Tsai-Sheng Gau, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Jiong-Ping Lu

Int. Cl.
CPC ...
H01L 21/308 (2006.01); G03F 7/20 (2006.01); G03F 1/00 (2012.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 21/306 (2006.01); H01L 21/302 (2006.01); H01L 21/033 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); G03F 1/144 (2013.01); G03F 7/70466 (2013.01); H01L 21/02071 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/302 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/30621 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76816 (2013.01); H01L 21/823431 (2013.01); H01L 21/845 (2013.01); H01L 27/1211 (2013.01); H01L 29/66795 (2013.01);
Abstract

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Find Patent Forward Citations

Loading…