Retention model with rtl-compatible default operating mode

Abstract

A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command. Restrictions prevent modification of the sequential block and path control signals and prevent use of generic input signals by the retention controller block.