Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

Abstract

Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.