The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Sep. 28, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Andrew Joseph Kelly, Hsinchu County, TW;

Yusuke Oniki, Hsinchu, TW;

Yasutoshi Okuno, Hsinchu, TW;

Ta-Chun Ma, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/088 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28229 (2013.01); H01L 21/0206 (2013.01); H01L 21/31111 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/513 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/02332 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.


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