The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Jul. 01, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher J. Larsen, Boise, ID (US);

David A. Daycock, Boise, ID (US);

Qian Tao, Boise, ID (US);

Saniya Rathod, Boise, ID (US);

Devesh K. Datta, Singapore, SG;

Srivardhan Gowda, Boise, ID (US);

Rithu K. Bhonsle, Boise, ID (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 8/12 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 16/06 (2006.01); G11C 19/28 (2006.01); H01L 27/11582 (2017.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 8/12 (2013.01); G06F 3/0644 (2013.01); G06F 3/0668 (2013.01); G06F 12/0223 (2013.01); G11C 16/06 (2013.01); G11C 19/28 (2013.01); H01L 27/11582 (2013.01); G11C 5/025 (2013.01); G11C 16/0483 (2013.01);
Abstract

Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.


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