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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10762269 B1

PDFFull Text
Date of Patent:
Sep. 01, 2020

Filed:

Jul. 01, 2019

Method of fabricating a semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Annie Lum, San Jose, CA (US);

Derek C. Tao, Fremont, CA (US);

Cheng Hung Lee, Hsinchu, TW;

Chung-Ji Lu, Fongyuan, TW;

Hong-Chen Cheng, Hsinchu, TW;

Vineet Kumar Agrawal, Santa Clara, CA (US);

Keun-Young Kim, Campbell, CA (US);

Pyong Yun Cho, Fremont, CA (US);

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Mohammed Alam

Int. Cl.
CPC ...
G06F 30/39 (2020.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); H01L 27/088 (2013.01); G06F 30/398 (2020.01); G06F 2119/18 (2020.01); H01L 27/0207 (2013.01); Y02P 90/265 (2015.11);
Abstract

A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Find Patent Forward Citations

Lum, Annie. (2020). Method of fabricating a semiconductor device (U.S. Patent No. 10762269). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10762269

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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