The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Oct. 12, 2018
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Chien-Fan Chen, Kaohsiung, TW;

Chien-Hao Wang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H05K 1/183 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 2224/04105 (2013.01); H01L 2924/11 (2013.01); H01L 2924/15153 (2013.01); H05K 2201/10 (2013.01);
Abstract

A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.


Find Patent Forward Citations

Loading…