The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Jan. 10, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuo-Chih Lai, Tainan, TW;

Shih-Min Chou, Tainan, TW;

Ko-Wei Lin, Taichung, TW;

Chin-Fu Lin, Tainan, TW;

Wei-Chuan Tsai, Changhua County, TW;

Chun-Yao Yang, Kaohsiung, TW;

Chia-Fu Cheng, Taipei, TW;

Yi-Syun Chou, Taipei, TW;

Wei Chen, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14609 (2013.01); H01L 21/7687 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 28/75 (2013.01);
Abstract

An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.


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