The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Dec. 21, 2018
Applicant:

Ningbo Semiconductor International Corporation, Ningbo, CN;

Inventors:

Hailong Luo, Ningbo, CN;

Clifford Ian Drowley, Ningbo, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80894 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06582 (2013.01);
Abstract

The present disclosure provides a wafer-level packaging method and a package structure. The wafer-level packaging method includes: providing a device wafer that contains a plurality of first chips, that each first chip contains a first electrode exposed at a wafer front surface of the device wafer; providing a plurality of second chips, that each second chip contains a second electrode exposed at a chip front surface of the each second chip, and a surface opposite to the chip front surface is a chip back surface; bonding the chip back surface of the each second chip to a portion of the wafer front surface of the device wafer between adjacent first chips of the plurality of first chips; forming insulating sidewalls on sidewalls of the plurality of second chips; and forming a conductive layer conformally covering the chip front surface, each insulating sidewall, and the wafer front surface.


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