The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Dec. 30, 2018
Applicant:

Ningbo Semiconductor International Corporation, Ningbo, CN;

Inventors:

Hu Shi, Ningbo, CN;

Mengbin Liu, Ningbo, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 2224/271 (2013.01); H01L 2224/27436 (2013.01); H01L 2224/27515 (2013.01); H01L 2224/27618 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/29034 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83048 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83862 (2013.01); H01L 2224/83951 (2013.01);
Abstract

A wafer-level packaging method includes providing a base substrate and providing first chips. A photolithographic bonding layer is formed on the base substrate or on the first chips. First vias are formed in the photolithographic bonding layer. The first chips are pre-bonded to the base substrate through a photolithographic bonding layer with each first chip corresponding to a first via. A thermal compression bonding process is used to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate. The base substrate is etched to form second vias through the base substrate with each second via connected to a first via to form a first conductive via. A first conductive plug is formed in the first conductive via to electrically connect to a corresponding first chip.


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