The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Jun. 10, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Pouya Hashemi, White Plains, NY (US);

Mahmoud Khojasteh, Poughkeepsie, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); B82Y 10/00 (2011.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); B82Y 10/00 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02543 (2013.01); H01L 21/02546 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/02603 (2013.01); H01L 21/30617 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1079 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66469 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/78618 (2013.01); H01L 29/78681 (2013.01); H01L 29/78696 (2013.01); H01L 21/02373 (2013.01); H01L 21/02458 (2013.01); H01L 21/02461 (2013.01); H01L 21/02507 (2013.01); H01L 21/02639 (2013.01);
Abstract

A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.


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