The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Aug. 13, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Furen Lin, Chengdu, CN;

Frank Baiocchi, Allentown, PA (US);

Haian Lin, Bethlehem, PA (US);

Yunlong Liu, Chengdu, CN;

Lark Liu, Chengdu, CN;

Wei Song, Chengdu, CN;

ZiQiang Zhao, Chengdu, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); G01V 1/38 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); G01V 1/16 (2006.01); G01V 1/18 (2006.01); G01V 1/24 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
G01V 1/3808 (2013.01); G01V 1/166 (2013.01); G01V 1/18 (2013.01); G01V 1/247 (2013.01); G01V 1/3852 (2013.01); H01L 29/0696 (2013.01); H01L 29/1087 (2013.01); H01L 29/402 (2013.01); H01L 29/4175 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 29/7823 (2013.01); H01L 29/7835 (2013.01); G01V 1/38 (2013.01); G01V 2210/1427 (2013.01); H01L 29/4238 (2013.01); Y10T 24/39 (2015.01);
Abstract

A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.


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