The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Sep. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu Fang Fu, Xinpu Township, TW;

Chi-Feng Huang, Zhubei, TW;

Chia-Chung Chen, Keelung, TW;

Victor Chiang Liang, Hsinchu, TW;

Fu-Huan Tsai, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H03K 3/03 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/1041 (2013.01); H01L 29/785 (2013.01); H01L 29/7835 (2013.01); H01L 21/823814 (2013.01); H03K 3/0315 (2013.01);
Abstract

A method includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method includes forming a first source/drain feature between the gate structure and the first edge structure; and a second source/drain feature between the gate structure and the second edge structure. A distance between the gate structure and the first source/drain feature is from about 1.5 to about 4.5 times greater than a distance between the gate structure and the second source/drain feature. The method includes implanting a buried channel in the semiconductor strip. A top surface of the buried channel is spaced from a top surface of the semiconductor strip. A bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature. A dopant concentration of the buried channel is highest under the gate structure.


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