The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Mar. 20, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andreas Meiser, Sauerlach, DE;

Anton Mauder, Kolbermoor, DE;

Roland Rupp, Lauf, DE;

Oana Julia Spulber, Neubiberg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0256 (2006.01); H01L 21/336 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/2251 (2013.01); H01L 29/0619 (2013.01); H01L 29/0865 (2013.01); H01L 29/1033 (2013.01); H01L 29/4236 (2013.01); H01L 29/66068 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device includes trench gate structures that extend from a first surface into a silicon carbide portion. A shielding region between a drift zone and the trench gate structures along a vertical direction orthogonal to the first surface forms an auxiliary pn junction with the drift zone. Channel regions and the trench gate structures are successively arranged along a first horizontal direction. The channel regions are arranged between a source region and a current spread region along a second horizontal direction orthogonal to the first horizontal direction. Portions of mesa sections between neighboring trench gate structures fully deplete at a gate voltage within an absolute maximum rating of the semiconductor device.


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