The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2020
Filed:
Apr. 03, 2017
Applicant:
Eplis Technologies Inc., Ottawa, CA;
Inventors:
Kangguo Cheng, Schenectady, NY (US);
Rama Divakaruni, Ossining, NY (US);
Assignee:
ELPIS TECHNOLOGIES INC., Ottawa, Ontario, CA;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 21/324 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/84 (2013.01); H01L 23/5283 (2013.01); H01L 29/0649 (2013.01); H01L 29/0843 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01);
Abstract
A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.