The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Jul. 18, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Burton Jesse Carpenter, Austin, TX (US);

Kim Roger Gauen, Noblesville, IN (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/62 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01); H04B 5/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/4952 (2013.01); H01L 23/5227 (2013.01); H01L 23/62 (2013.01); H01L 24/33 (2013.01); H01L 24/49 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 25/0652 (2013.01); H04B 5/005 (2013.01);
Abstract

A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.


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