The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Mar. 05, 2019
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Thomas Basler, Riemerling, DE;

Edward Fuergut, Dasing, DE;

Christian Kasztelan, Munich, DE;

Ralf Otremba, Kaufbeuren, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 23/40 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 23/24 (2013.01); H01L 23/36 (2013.01); H01L 23/3737 (2013.01); H01L 23/4006 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49861 (2013.01); H01L 24/37 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/074 (2013.01); H01L 23/4093 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 2224/293 (2013.01); H01L 2224/29294 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/37013 (2013.01); H01L 2224/401 (2013.01); H01L 2224/40227 (2013.01); H01L 2224/40247 (2013.01); H01L 2224/45099 (2013.01); H01L 2224/4846 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8384 (2013.01); H01L 2224/83825 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of manufacturing a semiconductor power package includes: embedding a power semiconductor chip in an encapsulation, the encapsulation forming a housing of the semiconductor power package; and extending a layer of a covering material over at least a part of an outer main surface of the encapsulation. The covering material has a thermal conductivity greater than a thermal conductivity of the material of the encapsulation and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.


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