The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Oct. 19, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Zhenxing Bi, Niskayuna, NY (US);

Muthumanickam Sankarapandian, Niskayuna, NY (US);

Richard A. Conti, Altamont, NY (US);

Michael P. Belyansky, Halfmoon, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31116 (2013.01); H01L 21/02318 (2013.01); H01L 21/02334 (2013.01); H01L 21/02337 (2013.01); H01L 21/02356 (2013.01); H01L 21/76224 (2013.01); H01L 21/76828 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 Å/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.


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