The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2020
Filed:
Dec. 19, 2018
Globalfoundries Inc., Grand Cayman, KY;
Hojin Kim, Clifton Park, NY (US);
Dongyue Yang, Ballston Lake, NY (US);
Dong-Ick Lee, Commack, NY (US);
Yue Zhou, San Jose, CA (US);
Jae Ho Joung, Cohoes, NY (US);
Gregory Costrini, Flanders, NJ (US);
El Mehdi Bazizi, San Jose, CA (US);
Dongsuk Park, Mechanicville, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.