The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2020
Filed:
Feb. 10, 2017
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;
Inventors:
Wen-Cheng Lo, Zhubei, TW;
Sun-Jay Chang, Hsinchu County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/0228 (2013.01); H01L 21/02299 (2013.01); H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 29/0847 (2013.01); H01L 29/785 (2013.01); H01L 29/7847 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 29/7853 (2013.01);
Abstract
Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.