The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Feb. 27, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Rouying Zhan, Chandler, AZ (US);

Jean-Philippe Laine, saint lys, FR;

Evgueniy Nikolov Stefanov, Vieille Toulouse, FR;

Alain Salles, Ramonville Saint Agne, FR;

Patrice Besse, Tournefeuille, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 27/02 (2006.01); H01L 29/74 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 29/7428 (2013.01); H02H 9/046 (2013.01);
Abstract

An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.


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