The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

May. 25, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Liu Chen, Oberhaching, DE;

Teck Sim Lee, Melaka, MY;

Jia Yi Wong, Melaka, MY;

Wei Han Koo, Melaka, MY;

Thomas Stoeck, Buxtehude, DE;

Gilles Delarozee, Gruenwald, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/492 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/433 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/498 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/36 (2013.01); H01L 23/4334 (2013.01); H01L 23/492 (2013.01); H01L 23/49513 (2013.01); H01L 23/49524 (2013.01); H01L 23/49551 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/3736 (2013.01); H01L 23/49861 (2013.01); H01L 2224/16245 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.


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