The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Aug. 23, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Sean X Lin, Watervliet, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Guoxiang Ning, Clifton Park, NY (US);

Lei Sun, Altamont, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); H01L 21/76804 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76871 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/585 (2013.01);
Abstract

A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.


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