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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10720533 B1

PDFFull Text
Date of Patent:
Jul. 21, 2020

Filed:

Sep. 07, 2018

Non-volatile memory device and method for manufacturing the same

Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chu-Chun Hsieh, Taichung, TW;

Tse-Mian Kuo, Taichung, TW;

Assignee:

WINBOND ELECTRONICS CORP., Taichung, TW;

Attorney:

Muncy, Geissler, Olds & Lowe, P.C.

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3215 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/0234 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/32155 (2013.01); H01L 21/76224 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66825 (2013.01); H01L 21/02164 (2013.01); H01L 21/32137 (2013.01);
Abstract

A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.

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